Programmable logic devices (PLDs) are a well-known type of programmable IC that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Programmable ICs are used in many applications, such as mobile, aerospace and defense applications, where power consumption is often a critical design issue. The dynamic power consumption of an electronic circuit contributes substantially to the overall power consumption. Current approaches for reducing dynamic power consumption may not provide the desired results, may be time-consuming or may complicate design considerations.
Partial reconfiguration of a programmable IC has been used to deactivate (or “put to sleep”) a module and thereby reduce dynamic power consumption. In this approach, the area of the programmable IC that is occupied by the module that is to be put to sleep is reconfigured with a “blank” module. The blank module is non-responsive to input signals so that flip-flops in the area of the programmable IC that is occupied by the blank module do not change state. The blank module approach requires storage for the blank bitstream and may require more time than is desirable for scenarios in which a short sleeping period is desired.
In another approach, dynamic power consumption may be reduced by gating the clock signal input to the portion(s) of the programmable IC occupied by the module to be put to sleep. This approach requires the designer to include clock gating logic as part of the overall design.